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this document is a general product descript ion and is subject to change without notic e. hynix semiconductor does not assume any responsibility for use of circuits descr ibed. no patent licenses are implied. rev. 1.5/ mar. 2008 1 hy5rs123235bfp 512mbit (16mx32) gddr3 sdram hy5rs123235bfp
rev. 1.5 / apr. 2008 2 hy5rs123235bfp revision history revision no. history draft date remark 0.1 defined target spec. apr. 2006 preliminary 0.2 1. cas lantency(12~15) are removed. 2. cas latency(12~15) change to reserved on page 11. 3. additive latency and low power mode in emrs are deleted on page 16. 4. tck_max changes from 3.3ns to 3ns. jun. 2006 preliminary 0.3 tck_max changes from 3ns to 3.3ns below cl10. july. 2006 preliminary 0.4 1. added idd values 2. changed ordering information with power supply july. 2006 preliminary 0.5 1. changed twr number at 1.2ghz speed on page 54 2. changed typo for ron on page 15 3. added note.48 on page 53 aug. 2006 preliminary 0.6 1. changed trrd from 16 to 13 and twtr from 8 to 10 at tck=0.8 2. inserted ac parameter value on 800mhz(tck=1.2) for reference on page 54 sep. 2006 preliminary 1.0 1. changed tdh/s from 140ps to 130ps on 1ghz 2. changed a vid(ac) value from 0.5/vddq+0.5 to 0.22/ vddq+0.3 (min/max) on page 46. oct. 2006 1.1 1. changed pkg bottom mold on page 59. 2. changed tras_max from 100k tck to 70kns on page 54. 3. revised typo. oct. 2006 1.2 revised appendix c about the boundary sacn test on page 62. nov. 2006 1.3 1. updated idd6 value on page 47. 2. inserted -18l instead of -2l and changed idd value about that. 3. revised the (-12)?s, (-1)?s and (-08)?s parameter value at table20 on page 54. apr. 2007 1.4 1. updated tfaw from 61 to 48 on page 54. 1.5 1. inserted the thermal characteristics table on page 44. mar.2008
rev. 1.5 / apr. 2008 3 hy5rs123235bfp description the hynix hy5rs123235 is a high-speed cmos, dynami c random-access memory containing 536,870,912 bits. the hynix hy5rs123235 is internally configured as a eight-bank dram. the hynix hy5rs123235 uses a double data rate architecture to achieve high-speed opreration. the double date rate architectu re is essentially a 4n-prefetch architecture, wi th an interface designed to transfer two data words per clock cycle at the i/o pin s. a single read or write access for the hynix hy5rs123235 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. read and write accesses to the hyni x hy5rs123235 is burst oriented; accesses start at a selected loca tions and continue for a programmed number of locations in a pr o- grammed sequence. accesses begin with the re gistration of an active command, which is then followed by a read of write com- mand. the address bits regi stered coincident with the active command are us ed to select the bank and row to be accessed (ba0,ba1, ba2 select the bank; a0-a11 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operatio n, the hynix hy5rs123235 must be ini- tialized. features note) above hynix p/n?s and their homogeneous subc omponents are rohs (& lead free) compliant ordering information part no. power supply clock frequency max data rate interface package hy5rs123235bfp-08 vdd/vddq=2.05v 1200mhz 2400mbps/pin pod_18 11mmx14mm 136ball fbga hy5rs123235bfp-1 1000mhz 2000mbps/pin hy5rs123235bfp-11 vdd/vddq=1.8v 900mhz 1800mbps/pin HY5RS123235BFP-14 700mhz 1400mbps/pin hy5rs123235bfp-2 500mhz 1000mbps/pin HY5RS123235BFP-14l vdd/vddq=1.5v 700mhz 1400mbps/pin pod_15 hy5rs123235bfp-18l 550mhz 1100mbps/pin ? 2.05v/ 1.8v/ 1.5v power supply supports (for more detail, please see the table 12 on page 43) ? single ended read strobe (rdqs) per byte ? single ended write strobe (wdqs) per byte ? internal, pipelined double-data-rate (ddr) architecture; two data accesses per clock cycle ?on die termination ? output driver strength adjustment by emrs ? calibrated output driver ? differential clock inputs (ck and ck#) ? commands entered on each positive ck edge ? rdqs edge-aligned with data for read; with wdqs center-aligned with data for write ? 8 internal banks for concurrent operation ? cas latency: 4~11 (clock) ? data mask (dm) for masking write data ? 4n prefetch ? programmable burst lengths: 4, 8 ? 32ms, 8k-cycle auto refresh ? auto precharge option ? auto refresh and self refresh modes ? 1.8v pseudo open drain i/o ? concurrent auto precharge support ? tras lockout support, active termination support ? programmable write latency(1, 2, 3, 4, 5, 6) ? boundary scan function with sen pin ? mirror function with mf pin
rev. 1.5 / apr. 2008 4 hy5rs123235bfp ballout configuration 1 2 3 4 5678 9 10 11 12 a vddq vdd vss zq mf vss vdd vddq b vssq dq0 dq1 vssq vssq dq9 dq8 vssq cvddq dq2 dq3 vddq vddq dq11 dq10 vddq d vssq wdqs0 rdqs0 vssq vssq rdqs1 w dqs1 vssq evddq dq4 dm0 vddq vddq dm1 dq12 vddq fvdd dq6 dq5 cas# cs# dq13 dq14 vdd g vss vssq dq7 ba0 ba1 dq15 vssq vss h vref a1 ras# cke we# ba2 a5 vref j vss nc rfu vddq vddq ck# ck vss k vdd a10 a2 a0 a4 a6 a8/ap vdd l vss vssq dq25 a11 a7 dq17 vssq vss mvdd dq24 dq27 a3 a9 dq19 dq16 vdd nvddq dq26 dm3 vddq vddq dm2 dq18 vddq p vssq wdqs3 rdqs3 vssq vssq rdqs2 w dqs2 vssq rvddq dq28 dq29 vddq vddq dq21 dq20 vddq t vssq dq30 dq31 vssq vssq dq23 dq22 vssq u vddq vdd vss sen res vss vdd vddq 16m x 32 configuration 2m x 32 x 8 banks refresh count 8 k bank address ba0 - ba2 row address a0~a11 column address a0~a7, a9 ap flag a8
rev. 1.5 / apr. 2008 5 hy5rs123235bfp functional block diagram 8banks x 2mbit x 32 i/o double data rate synchronous dram bank0 row address latch & decoder bank5 bank6 bank7 bank0 memory array (4096x512x128) sense amplifiers bank5 bank6 bank7 column decoder bank control logic column address counter latch dll drvrs mux ccl0, ccl1 ck/ ck# data 32 32 32 32 32 read latch 128 4 4 rcvrs 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 16 128 mask data ck/ck# 128 wri te fifo & drivers ck out ck in input registers i/o gating dm mask logic bank0 row address latch & decoder bank1 bank2 bank3 bank0 memory array (4096x512x128) sense amplifiers bank1 bank2 bank3 128 row address mux refresh counter 12 12 7 2 col0, col1 40% 66,536 512 (x128) control logic command decode mode registers address register 3 3 12 15 9 15 cke ck ck# cs# ras# cas# we# a0~a11 ba0- ba2 4 ck/ck# dq0~dq31 wdqs( 0~3) dm(0~3) bank4 bank4
rev. 1.5 / apr. 2008 6 hy5rs123235bfp ballout descriptions fbga ballout symbol type description j10, j11 ck, ck# input clock: ck and ck# are differential clock inputs. all address and con- trol input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. h4 cke input clock enable: cke high activates and cke low deactivates the inter- nal clock, input buffers and output drivers. taking cke low provides precharge power-down and self refresh operations(all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry and exit, and for self refresh entry. cke is asynchronous for se lf refresh exit and for disabling the outputs. cke must be maintained high throughout read and write accesses. input buffers (excluding ck, ck# and cke) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. f9 cs# input chip select: cs# enables (register ed low)and disables (registered high) the command decoder. all co mmands are masked when cs# is registered high. cs# provides for ex ternal bank selection on systems with multiple banks. cs# is considered part of the command code. h3, f4, h9 ras#, cas#, we# input command inputs: ras#, cas# and we#(along with cs#) define the command being entered. e(3, 10), n(3, 10) dm0-dm3 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sample d high along with that input data during a write access. dm is sampled on rising and falling edges of wdqs. g(4, 9), h10 ba0 - ba2 input bank address inputs: ba0 and ba2 define to which bank an active, read, write or precharge command is being applied. h(2, 11), k(2-4, 9-11), l(4, 9), m(4, 9) a0-a11 input address inputs: provide the row a ddress for active commands, and the column address and auto pr echarge bit(a8) for read/write commands, to select one location out of the memory array in the respective bank. a8 sampled during a precharge command deter- mines whether the precharge applie s to one bank (a8 low, bank selected by ba0 - ba2 ) or all banks (a8 high). the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode register) is loaded during the load mode register com- mand. b(2, 3), c(2, 3), e2, f(2, 3), g3,b(10, 11), c(10, 11), e11, f(10, 11), g10, l10, m(10, 11), n11, r(10, 11), t(10,11), l3, m(2, 3), n2,r(2, 3), t(2, 3) dq0-31 i/o data input/output: d(3, 10), p(3, 10) rdqs0-3 output read data strobe: output with read data. rdqs is edge-aligned with read data. d(2, 11), p(2, 11) wdqs0-3 input write data strobe: input with write data. wdqs is center aligned to the input data. u4 sen input scan enable pin. logic high would enable scan mode. should be tied to gnd when not in use. this pin is a cmos input. j(2, 3) nc/rfu no connect
rev. 1.5 / apr. 2008 7 hy5rs123235bfp ballout descriptions -c ontinue mirror function the gddr3 sdram provides a mirror function(mf) ball to change the physical location of the control lines and all address lines, assisting in routing devices back to back. the mf ball will affect ras#, cas#, we#, cs# and cke on balls h3, f4, h9, f9 and h4 respectively and a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, ba0, ba1 and ba2 on balls k4, h2, k3, m4, k9, h11, k10, l9, k11, m9, k2, l4, g4, g9 and h10 respectively and only detects a dc input. the mf ball should be tied directly to vss of vdd dependin g on the control line orientation desired. when mf ball is tied low the ball orientation is as follows. ras#-h3, cas#-f4, we#-h9, cs#-f9, cke-h4, a0-k4, a1-h2, a2-k3, a3- m4, a4-k9, a5-h11, a6-k10, a7-l9, a8-k11, a9-m9, a10-k2, a11-l4 , ba0-g4, ba1-g9 and ba2-h10. the high condition on the mf ball will change the location of the control balls as follows; cs#-f4, cas#-f9, ras#-h10, we#-h4, cke-h9, a0-k9, a1-h11, a2-k10 , a3-m9, a4-k4, a5-h2, a6-k3, a7-l4, a8-k2, a9-m4, a10-k11, a11-l9, ba0-g9, ba1-g4 and ba2-h3. this mirror fuction does not work under boundary scan test condition. mirror function signal mapping fbga ball out symbol type description a(1, 12), c(1, 4, 9, 12), j(4, 9), n(1, 4, 9, 12), r(1, 4, 9, 12), u(1, 12) vddq supply dq power supply: +1.8v. isolated on the die for improved noise immunity. b(1, 4, 9, 12), d(1, 4, 9, 12), g(2, 11), l(2, 11), p(1, 4, 9, 12), t(1, 4, 9, 12) vssq supply dq ground: isolated on the die for improved noise immu- nity. a(2, 11), f(1, 12), m(1, 12), u(2, 11) k(1, 12) vdd supply power supply: +1.8v. a(3, 10), g(1, 12), l(1, 12), u(3, 10) j(1, 12) vss supply ground h(1, 12) vref supply reference voltage. a9 mf reference mirror function for clamshell mounting of drams a4 zq reference external reference pin for autocalibration. it should be connected to rq(=240 ?) u9 res reference reset pin. the res pin is a vdd cmos input. pin mf logic state high low ras# h10 h3 cas# f9 f4 we# h4 h9 cs# f4 f9 cke h9 h4 a0 k9 k4 a1 h11 h2 a2 k10 k3 a3 m9 m4 a4 k4 k9 a5 h2 h11 a6 k3 k10 a7 l4 l9 a8 k2 k11 a9 m4 m9 a10 k11 k2 a11 l9 l4 ba0 g9 g4 ba1 g4 g9 ba2 h3 h10
rev. 1.5 / apr. 2008 8 hy5rs123235bfp gddr3 initialization and power up gddr3 sdrams must be powered up and initialized in a predefined manner. oper ational procedures other than those specified may result in undefined operation. power must be first applied to vdd and vddq simultaneously or vdd first and vddq later, and then to vref. vref can be applied any time after vddq. once power has been applied and the clocks are stabl e the gddr3 device requires 200us before the res pin transitions to high. upon power-up and after the clock is stable, the on-die ter- mination value for the address and control pins will be set, based on the state of cke when the res pin transitions from low to high. on the rising edge of res, the cke pin is latched to de termine the on die termination value for the address and control l ines. if cke is sampled at a logic low then the on die termination will be set to 1/2 of zq and, if cke is sampled logic high then th e on die termination will be set to the same value as zq. cke must meet tats and tath on the rising of res to set the on die termina tion for address and control lines. once tath is met, set cke to high. an additional 200us is required for the address and command o n die terminations to calibrate and update. res must be maintained at a logic low-level value and cs# must be maintained high, during the first stage of power-up to ensure that the dq outputs will be in a high-z state( un-terminated ). after the res pin transitions from low to high, wait until a 200us delay is satisfied. issue deselect on the command bus during this time. issue a precharge all command. ne xt a load mode register command must be issued for the extended mode regis- ter (ba1 low and ba0 high) to activate th e dll and set operating parameters, followed by the load mode register command (ba0/ba1 both low) to reset the dll and to program the rest of the operating parameters. 5k clock cycles are required between t he dll reset and any read command to allow the dll to lock. a precharge all command should then be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be issued. following these requ irements, the gddr3 sdram is ready for nor- mal operation. 5 5e 5f 5d 5c 5b 5 5gp /01 "$5 "3 "3 13& -.3 -.3 13& 73&' 7%%2 7%% "5) "54 3" $0%& $0%& 3" 3" $0%& $0%& 3%24 #" #" " " " " " %. $0.."/% $,& 3&4&5 $, $, %2 8%24 5vt )*() u31 1pxfsvq7%%boe $mpdltubcmf #"0) #"- u*4 "--#"/,4 u$) u$- "--#"/,4 u*4 u*4 u*4 u*) u*) u*) u*) u*) u*4 #"0- #") )*() )*() 5vt 5vt u.3% u31 u.3% u3'$ u3'$ 1sfdibshf"mm #bolt -pbe&yufoefe .pef3ftjtups -pbe.pef3ftjtups %--3ftfu 1sfdibshf"mm #bolt tu"vup 3fgsfti oe"vup 3fgsfti
rev. 1.5 / apr. 2008 9 hy5rs123235bfp odt updating the gddr3 sdram uses programmable impedance output buffers. this allows a user to match the driver impedance to the system. to adjust the impedance, an external prec ision resistor (rq) is connected between th e zq pin and vssq. the value of the resisto r must be six times the desired driver impedance. for example, a 240 ? . resistor is required for an output impedance of 40 ? . to ensure that output impedance is one-sixth the value of rq (within 10 percent) , rq should be in the range of 210 ? . to 270 ? . (30 ? . - 50 ? . output impedance). ck and ck# are not internal ly terminated. ck and ck# will be terminated on the system module using external 1% resistors. the output impedance and on die termination is updated during ev ery auto refrresh commands to compensate for variations in supply voltage and temperature. the output impedance updates ar e transparent to the system. impedance updates do not affect device operation, and all datash eet timings and current specificat ions are met during an update. a maximum of eight auto refresh commands can be posted to any given gddr3 sdra m, meaning that th e maximum absolute interval between any auto refresh command and the next auto refresh command is 8 x 3.9us (31.2us). this maximum abso- lute interval guarantees that the output drivers and the on die terminations of gddr3 sdrams are recalibrated often enough to k eep the impedance characteri stics of those within the specified boundaries. odt control bus snooping for read commands other than cs# is used to control the on die termination in the dual load configuration. the gddr3 sgram will disable the dq and rdqs on die termination when a read command is detected regardless of the state of cs#. the on die termination is disabled x clocks after the read command where x equals cl-1 and stay off for a duration of bl/2+2ck. in a two-rank system, both dram devices snoop the bus for read comma nds to either device and both will disable the on die termina- tion, for the dq and dqs pins if a read command is detected. the on die termination for all other pins on the device is always turned-on for both a single-rank system and a dual-rank system unl ess it is turned off in the emrs. only dq,wdqs and dm pins ca n turn off through the emrs.
rev. 1.5 / apr. 2008 10 hy5rs123235bfp mode register definition the mode register is used to define the specific mode of operation of the gddr3 sdram. this definition includes the selection of a burst length, cas latency, write latency, and operating mode, as shown in figure 3, mode register definition, on page 11. the mode register is programmed via the mode register set command (with ba0=0, ba1=0 and ba2=0) and will retain the stored information until it is programmed again or the device loses po wer (except for bit a8, which is self-clearing). re-programming the mode register will not alter the contents of the memory. the mode register must be loaded (reloa ded) when all banks are idle an d no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. violating e ither of these requirements will result in unspecified operation. mode register bits a2-a0 specify the burst length; a3 specifie s the type of burst (sequential) ; a4-a6 specify the cas latency; a7 is a test mode; a8 specifies the operating mode; and a9-a11 specifiy the write latency.
rev. 1.5 / apr. 2008 11 hy5rs123235bfp figure 3: mode re gister definition ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 wl dr tm cas latency bt cl burst length a1 a0 burst length 00 reserved 01 reserved 10 4 11 8 a11 a10 a9 write latency 000 reserved 001 1 010 2 011 3 100 4 101 5 110 6 111 reserved a7 test mode 0normal 1yes a3 burst type 0 sequential 1 reserved a2 a6 a5 a4 cas latency 0000 8 0001 9 0010 10 0011 11 0100 4 0101 5 0110 6 0111 7 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved a8 dll reset 0no 1 yes note: 1) the dll reset command is self-clearing.
rev. 1.5 / apr. 2008 12 hy5rs123235bfp burst length read and write accesses to th e gddr3 sdram are burst-oriented, with the burst le ngth being programmable, as shown in figure3, mode register definition. the burst length determines the maximu m number of column locations that can be accessed for a given read or write command. burst lengths of 4 or 8 locations are available for the sequential burst type. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a2. ai when the burst length is set to four and by a3. ai when the burst length is set to eight(where ai is the most significant column address bit for a given configuration). the remaining(least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read an d write bursts. burst type accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit a3. this device does not support the interleaved burst mode found in ddr sdram devices. the ordering of accesses within a burst is determined by the burst length, the burst type, and the st arting column address, as shown in table3. table 3: burst definition note: 1. for a burst length of four, a2-a7 select the block of four burst; a0-a1 select the starting column within the block and must be set to zero. 2. for a burst length of eight, a3-a7 select the of eight burst; a0-a2 select the starting column within the block. burst 1, 2 length starting column address order of accesses within a burst type=sequential 4 a1 a0 0 0 0-1-2-3 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 1 0 0 4-5-6-7-0-1-2-3
rev. 1.5 / apr. 2008 13 hy5rs123235bfp cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of out- put data. the latency can be set to 7 1 clocks, as shown in figure 4, cas latency, on page 13. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. table4 indicates the operating frequencies at which each cas latency setting can be used. for the proper op eration, do not change the cl without dll reset. or proper cl should be set with dll reset code reserved states should not be used as unknown operation or incompatibility with future versions may result. table 4: cas latency figure 4: cas latency allowable operating frequency (mhz) speed cl=11 cl=10 cl=9 cl=7 -08 <=1200 -1 <=1000 -11 <=900 -14(l) <=700 -18(l) <=550 -2 <=500
rev. 1.5 / apr. 2008 14 hy5rs123235bfp write latency the write latency (wl) is the delay, in clock cycles ,between the registration of a write command and the availability of the first bit of input data as shown in figure5. the latency can be set from 1 to 6 clocks depending on the operating frequency and desired current draw. when the write latencies are set to 1 or 4 clocks, the input receivers never turn off, in turn, raising the opera ting power. when the write latency is set to 5 or 6 clocks the input receivers turn on when the write command is registered. if a write com- mand is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 5: write latency test mode the normal operating mode is selected by issuing a mode register set command with bit a7 set to zero, and bits a0~a6 and a8~a11 set to the desired values. test mode is initiated by issuing a mode register set command with bit a7 set to one, and bits a0~a6 and a8~a11 set to the desired values. test mode funtions are specific to each dram vendor and their exact function are hid- den from the user. dll reset the normal operating mode is selected by issuing a mode register set command with bit a8 set to zero, and bits a0~a7 and a9~a11 set to the desired values. a dll reset is initiated by issuing a mode register set command with bit a8 set to one, and b its a0~a7 and a9~a11 set to the desired values. wh en a dll reset is complete the gddr3 sdram reset bit, a8 of the mode register is self clearing (i.e.automatically se t to a zero by the dram). test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
rev. 1.5 / apr. 2008 15 hy5rs123235bfp extended mode register the extended mode regi ster controls functions beyond those controlled by the mode register; these additional func tions are dll enable/disable, drive strength, data termination, vendor id. these functions are controlled via the bits shown in figure 6, extended mode register definition. the extended mode register is programmed via the load mode register command to the mode register (with ba0 = 1, ba1 = 0 and ba2=0) and will retain the stored information until it is programmed again or the device loses power. the enabling of the dll should always be followe d by a load mode register command to the mode register (ba0/ba1 both low) to reset the dll.the extended mode re gister must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating an y subsequent operation. violating either of these requirements could result in unspec- ified operation. figure 6: extended mode register definition note: 1. the dt disable function disables all pins. 2. the default setting at power up for a3,a2 is 10 or 11 3. if the user activates bits in the extended mode regi ster in an optional field, device will work improperly. 4. the optional values of the drive strength (a1,a0) are only targets and can be determined by the dram vendor. 5. wr_a (write recovery time for autoprecha rge) in clock cycles is calculated by dividing twr (in ns) and rounding up to the ne xt integer (wr[cycles] = twr(ns)/tck(ns)). the mode register must be programmed to this value. 6. default value in c/a termination is determined by ck e status at the rising edge of reset during power-up. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 term vid ron 0 twr dll twr dt dz a6 dll enable 0enable 1disable a10 vendor id 0off 1on a1 a0 drive strength 00 auto cal 01 30 10 40 1 1 50(48) a3 a2 data termination 00 dt disabled 01 res 1 0 1/4 rq 1 1 1/2 rq ron of pull-up a9 ron 040 160 a7 a5 a4 twr 000 12 001 14 010 5 011 6 100 7 101 8 110 9 111 10 a11 c/a termination 0default 1half of default
rev. 1.5 / apr. 2008 16 hy5rs123235bfp dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after disabling the dll for debugging or evaluation. (when the device exits self refresh mode, the dll is enabled automat- ically.) any time the dll is enabled, 5k clock cycles must occur before a read command can be issued. twr(wr_a) the value of twr in the ac parametrics table on page 49 of this specification is loaded into register bits 5 and 4. the wr_a (write recovery time for autoprecharge) in clock cycles is calculated by dividing twr (in ns) and rounding up to the next integer (wr[ cycles] = twr(ns)/tck(ns)). the mode register must be programmed to this value. data termination the data termination value is used to define the value for the on die termination for the dq, dm, and wdqs pins. the gddr3 device supports one-quarter zq and one-ha lf zq termination for a nominal 60 ? or 120 ? set with bit a3 and a2 during an emrs command for a single- or dual-loaded system. data driver impedance the data driver impedance, dz, is used to determine the value of the data drivers impedance. when auto calibration is used the data driver impedance is set to 1/6 zq and it?s tolerance is de termined by the calibration accuracy of the device. when any oth er value is selected the target impedance is set nominally to the se lected impedance. however, the accuracy is now determined by t he device?s specific proces s corner, applied voltage and operating temperature.
rev. 1.5 / apr. 2008 17 hy5rs123235bfp manufacturers vendor code identifi- cation the manufacturers vendor code, v, is selected by issuing an extended mode register set command with bits a10 set to 1, and bits a0-a9 and a11 set to the desired values. when the v function is enabled the gddr3 sdram will provide its manufac- turers vendor code on dq[3:0] and revision identification on dq[7:4]. the code will be driven onto the dq bus after tidon with respect to the emrs that set a10 to 1. the dq bus will be continuously driven until an emrs write sets a10 back to 0. the dq bus will be in a hi-z stat e after tidoff. the code can be sampled by the controller after waiting tidon max and before tidoff min. table 5: vendor ids vendor dq(3:0) reserved 0 samsung 1 infineon 2 elpida 3 etron 4 nanya 5 hynix 6 mosel 7 winbond 8 esmt 9 reserved a reserved b reserved c reserved d reserved e micron f
rev. 1.5 / apr. 2008 18 hy5rs123235bfp clock frequency change sequence during the device operation not only clock frequency but also vdd change sequence as below both existing tck and desired tck are in dll-on mode - change frequency from existing frequency to desired frequency - issue precharge all banks command - issue mrs command to reset the dll while other fields are valid and required 5k tck to lock the dll - issue precharge all banks command. issue at least auto-refresh command existing tck is in dll-on mode while desired tck is in dll-off mode - issue precharge all banks command - issue emrs command to disable the dll - issue precharge all banks command - change the frequency from existing to desired. - issue auto-refresh command at least two. issue mrs command clock frequency change in case existing tck is in dll-off mode while desired tck is in dll-on mode - issue precharge all banks command and issue emrs command to disable the dll. - issue precharge all banks command. - change the clock frequency from existing to desired - issue precharge all banks command. - issue emrs command to enable the dll - issue mrs command to reset the dll and required 5k tck to lock the dll. - issue precharge all banks command. - issue auto-refresh command at least two $, $, $0.."/% /01 /01 /01 13& /01 /01 13& /01 "3 u'$)( .34 /01 /01 'sfrvfodz $ibohf u31 u.3% "mm#bolt 1sfdibsh f %-- 3ftfu "mm#bolt 1sfdibsh f u$, %--mpdljohujnf
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rev. 1.5 / apr. 2008 19 hy5rs123235bfp
rev. 1.5 / apr. 2008 20 hy5rs123235bfp commands table6 provides a quick reference of available commands, followe d by a description of each command. two additional truth table s appear following the operation sect ion; these tables provide curren t state/next state information. table 6: truth table - commands note: 1 table 7: truth tabl e 2 - dm operation note: 1. cke is high for all command s shown except self refresh. 2. ba0-ba1 select either the mode regist er or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 select extended mode register; other combin ations of ba0.ba1 are reserved). a0-a11 provide the opcode to b e written to the selected mode register. 3. ba0-ba2 provide bank address and a0-a11 provide row address. 4. ba0-ba2 provide bank address; a0-a7 and a9 provide colu mn address; a8 high enable s the auto precharge feature (non-persistent), and a8 low disables the auto precharge feature. 5. a8 low: ba0-ba2 determine which bank is precharged. a8 high: all banks are precharged and ba0-ba2 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all in puts and i/os are don?t care except for cke. 8. deselect and nop are f unctionally interchangeable. 9. used to mask write da ta; provided coincident with the corresponding data. 10. used for bus snooping when the dq termination is set to 120 ohms in the emr and cannot be used during power-down or self refresh. name (function) cs# ras# cas# we# addr notes deselect (nop) h x x x x 8 no operation (nop) l h h h x 8 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) l h l h bank/col 4 write (select bank and column, an d start write burst) l h l l bank/col 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (enter self refresh mode) lllh x 6, 7 load mode register l l l l op-code 2 data terminator disable x h l h x 10 name (function) dm dqs notes write enable l valid 9 write inhibit h x 8
rev. 1.5 / apr. 2008 21 hy5rs123235bfp deselect the deselect function (cs# high) prev ents new commands from being executed by the gddr3 sdram. the gddr3 sdram is effectively deselected. operations al ready in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected gddr3 sdram to perform a nop(cs# low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode registers are loaded via inputs a0~a11. see mode register descriptions in the register definition section. the load mode register command can only be issued when all banks are idle, and a subsequent executab le command cannot be issued until tmrd is met. active the active command is used to open (or activate) a row in a pa rticular bank for a subsequent access. the value on the ba0~ba2 inputs selects the bank, and the address provided on inputs a0~a 11 selects the row. this row re mains active (or open) for acces ses until a precharge command is issued to that bank. a precharge co mmand must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0~ba2 inputs selects the bank, a nd the address provided on inputs a0~a7, a9 selects the starting column location. the value on input a8 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0~ba2 inputs selects the bank, and the address provided on inputs a0~a7, a9 selects the starting column location. the value on input a8 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the mem- ory array subject to the dm input logic leve l appearing coincident with the data. if a given dm signal is re gistered low, the c orre- sponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will b e available for a subsequent row access a spec ified time (trp) after the precharge command is issued. input a8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0.ba2 select the bank. otherwise, ba0. ba2 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank (idle state) or if the previously open row i s already in the process of precharging.
rev. 1.5 / apr. 2008 22 hy5rs123235bfp auto precharge auto precharge is a feature th at performs the same individual-bank precharge function described above but without requiring an explicit command. this is accomplished by using a8 to enable auto precharge in conjunction with a specific read or write com- mand. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon comple- tion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual r ead or write command. auto precharge ensures that th e precharge is initiated at the earliest valid stage within a burst. this ?earlies t valid stage? is determined as if an explicit precharge command was issued at the earliest possible time, without violating tras min, as described for each burst type in the operation section of this data sheet. the user must not issue another command to the same bank until the precharge time (trp) is completed. auto refresh the addressing is generated by the internal refresh controller. this makes the address bits a do n?t care during an auto refres h command. the 512mb x32 gddr3 sdram requires auto refresh cycles at an average interval of 3.9us (maximum). a maximum of eight auto refresh commands can be posted to any given gddr3 sdram, meaning that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 x 3.9us (35.1us). this maximum absolute interval allows gddr3 sdram output drivers to automatically recalibrate to comp ensate for voltage and temperat ure changes. auto refresh is used during normal operation of the gddr 3 sdram and is analog ous to cas#-before-ras# (cbr) refresh in fpm/edo drams.this command is nonpersistent, so it must be issued each time a refresh is required. self refresh the self refresh command can be used to retain data in the gddr3 sdram, even if the rest of the system is powered down. when in the self refresh mode, the gddr3 sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled(low). the dll is automatically disabled upon entering self refresh and is automatically enabled and reset upon exit ing self refresh. the on-die termination is also disabled upon entering self refres h except for cke and enabled upon exiting self refresh. (5k clock cycles must then occur before a read command can be issued). input signals except cke are ?don?t care? during self refresh. the procedure for exiting self refresh requires a sequence of co m- mands. first, ck and ck# must be stable prior to cke going back high. once cke is high, the gddr3 sdram must have nop com- mands issued for txsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements and output calibration is to apply nops for 1000 clock cycles before applying any oth er command to allow the dl l to lock and the output drivers to recalibrate. if the gddr3 device enters self refresh with the dll di s- abled the gddr3 device will exit se lf refresh with the dll disabled. data terminator disable (bus snooping for read commands) bus snooping for read commands other than cs# is used to cont rol the on-die termination in the dual load configuration. the gddr3 sdram will disable the on-die termination when a read command is detected, regardless of the state of cs#, when the odt for the dq pins are set for dual loads (120 ? ).the on-die termination is disabled x clocks after the read command where x equals cl-1 and stay off for a duration of bl/2 +2ck, as shown in figure8, data termination disable timing on page15. in a two-rank sys- tem, both dram devices snoop the bus for read commands to either device and both will disable the on-die termination if a read command is detected. the on-die termination for all other pins on the device are always turned-on for bo th a single-rank system and a dual-rank system. boundary scan test mode the 512mb gddr3 incorporates a modified boundary scan test mode as an optional feature. this mode doesn?t operate in accor- dance with ieee standard 1149.11990. to save th e current gddr3 ballout, this mode will scan the parallel data input and output the scanned data through wdqs0 pin controlled by an addon pin, sen which is located at u4 of 136 ball package. you can find the detailed descriptions of this feature on appendix c (page 62).
rev. 1.5 / apr. 2008 23 hy5rs123235bfp figure 8: data termi nation disable timing note: 1. do n = data-out from column n. 2. burst length = 4. 3. three subsequent elements of data-out a ppear in the specified order following do n. 4. shown with nominal tac and tdqsq. 5. rdqs will start driving high one-half clock cycle prior to the first falling edge. 6. the data terminators are disabled starting at cl - 1 and the duration is bl/2 + 2ck. 7. reads to either rank disable both ranks? te rmination regardless of the logic level of cs#.
rev. 1.5 / apr. 2008 24 hy5rs123235bfp operations bank/row activation before any read or write commands can be issued to a bank within the gddr3 device, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated, as shown in figure 9, activating a spe- cific row in a specific bank. after a row is opened with an active com- mand, a read or write command may be issued to that row, subject to the trcd specification. trcd min should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a trcd specification of 15ns with a 550 mhz clock(1.8ns period) results in 7.5 clocks rounded to 8. this is reflected in figure 10, example: meeting trcd, which overs any cases where 7 < trcdmin/tck <= 8. the same procedure is used to convert other specificat ion limits from time units to clock cycles. a subse- quent active command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). the minimum time interval between su ccessive active commands to the same bank is defined by trc. a subsequent active command to another bank can be issued while the first bank is being accessed,which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by trrd. figure 9: activating a specific row in a specific bank figure 10: example: meeting trcd
rev. 1.5 / apr. 2008 25 hy5rs123235bfp read timing read burst is initiated with a read command. the starting column an d bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access with the a8 pin. if auto precharge is enabled, the row being accessed is precha rged at the completion of the burst after tras min has been met. during read bursts, the first valid data-out element from the starting column address will be available following the cas laten cy after the read command. each subsequent data-out element will be valid nominally at the next positive or negative rdqs edges. the gddr3 sdram drives the output data edge aligned to rdqs. and all outputs, i.e. dqs and rdqs, are also edge aligne d to the clock . prior to the first valid rdqs rising edge, a cycle is driven and specified as the read preamble. the preamble consists of a hal f cycle high followed by a half cycle low driven by the gddr3 sdram. the cycle on rdqs consisting of a half cycle low coincident with t he last data-out element followed by a half cycle high is known as the read postamble, and it will be driven by the sdram. the sdr am toggles rdqs only when it is driving valid data out onto on the bus. upon completion of a burst, assuming no other command has been in itiated; the dqs and rdqs will go to be in hi-z state. vddq due to the on die termination. long as the bus turn around time is met. read data cannot be terminated or truncated. a precharge can also be issued to the sdram with the same timing restriction as the new read command if tras is met as shown in figure 17, read to precharge, on page 29. a write can be issu ed any time after a read command as long as the bus turn around time is met as shown in figure 16, read to write, on page 28. read data cannot be terminated or truncated
rev. 1.5 / apr. 2008 26 hy5rs123235bfp figure 12: read burst note: 1. do n = data-out from column n. 2. burst length = 4. 3. three subsequent elements of data-out a ppear in the specified order following do n. 4. shown with nominal tac and tdqsq. 5. rdqs will start driving high one-half clock cycle prior to the first falling edge.
rev. 1.5 / apr. 2008 27 hy5rs123235bfp figure 13: consecutive read bursts note: 1. do n (or b) = data-out from column n (or column b). 2. burst length = 4 3. three subsequent elements of data-out a ppear in the programmed order following do n. 4. three subsequent elements of data-out appear in the programmed order following do b. 5. shown with nominal tac, and tdqsq. 6. example applies only when read commands are issued to same device. 7. rdqs will start driving high one half clock cycle prior to the first falling edge of rdqs.
rev. 1.5 / apr. 2008 28 hy5rs123235bfp figure 14: non-consecutive read bursts note: 1. do n (or b) = data-out from column n (or column b). 2. burst length = 4. 3. three subsequent elements of data-out a ppear in the programmed order following do n. 4. three subsequent elements of data-out appear in the programmed order following do b. 5. shown with nominal tac and tdqsq. 6. example applies when read commands are issued to different devices or nonconsecutive reads. 7. rdqs will start driving high one-half clock cycle prior to the first falling edge of rdqs.
rev. 1.5 / apr. 2008 29 hy5rs123235bfp figure 15: random read accesses note: 1. do n (or x or b or g) = data-out from colu mn n (or column x or co lumn b or column g). 2. burst length = 4. 3. reads are to an active row in any banks. 4. shown with nominal tac and tdqsq. 5. rdqs will start driving high one-half clock cycle prior to the first falling edge of rdqs.
rev. 1.5 / apr. 2008 30 hy5rs123235bfp figure 16: read to write note: 1. dq n = data-out from column n. 2. di b = data-in from column b. 3. shown with nominal tac, tdqsq and tdqss. 4. read preamble consists of a half cycle high followed by a half cycle low driven by device 5. write data cannot be driven onto the dq bus for 2 clocks after the read data is off the bus. 6. the timing diagram covers a read to a write command from diffe rent device, different bank or the same row in the same bank. t0 t7 ck ck# read nop write nop nop nop bank col n bank col b nop cmd add rdqs wdqs dq t8 t9 t10 t11 t12 cl=7, bl=4, wl=3 on-die termination off on-die termination on odt on odt dq n di b wl=3 cl=7
rev. 1.5 / apr. 2008 31 hy5rs123235bfp figure 17: read to precharge note: 1. do n = data-out from column n. 2. burst length = 4. 3. three subsequent elements of data-out a ppear in the programmed order following do n. 4. shown with nominal tac and tdqsq. 5. read to precharge equals two clocks, which enables two data pairs of data-out. 6. pre = precharge command; act = active command. 7. rdqs will start driving high one-half clock cycle prior to the first falling edge of rdqs .
rev. 1.5 / apr. 2008 32 hy5rs123235bfp write timing write burst is initiated with a write command. the starting column and bank addresses are provided with the write comma nd, and auto precharge is ei ther enabled or disabled for that access with the a8 pin. if auto precharge is en abled, the row being accessed is precharged at the completion of the bu rst. during write bursts, the first valid data-in element will be registered on the rising edge of wdqs following the write latency set in the mode register and subsequent data elements will be register ed on successive edges of wdqs. prior to the first valid wdqs ri sing edge, a cycle is needed and specified as the write preamble. the preamble consists of a half cycle high followed by a half cycl e low driven by the controller. the cycle on wdqs following the last data-in element is known as the write postamble and must be driv en high by the controller, it can not be left to float high using the on die termination. the wdqs should only toggle on data tran sfers. the time between the write command and the first valid rising edge of wdqs (tdqss) is specified relative to the write latency ( wl - 0.25tck and wl + 0.25tck). al l of the write diagrams show the nominal case , and where the two extreme cases (i.e., tdqss [min] and tdqss [max]) might not be intuitive, they have also been included. upon completion of a burst, assuming no other com- mand has been initiated, the dqs should remain hi-z and any additional input data will be ignored. data for any write burst may not be truncated with any subsequent command. a subsequent write command can be issued on any positive edge of clock following the previous write command assuming the previous burst has completed. the subsequent write command can be issued x cycles afte r the previous write command, where x equals the number of desired nibbles x2 (nib- bles are required by 4n-prefetch architectu re) i.e. bl/2. a subsequent read command ca n be issued once twtr is met or a subse- quent precharge command can be issued once twr is met. af ter the precharge command, a subsequent command to the same bank cannot be issued until trp is met.
rev. 1.5 / apr. 2008 33 hy5rs123235bfp figure 19: write burst note: 1. di b = data-in for column b. 2. three subsequent elements of data-in are applied in the specified order following di b. 3. a burst of 4 is shown. 4. a8 is low with the write comm and (auto precharge is disabled). 5. write latency is set to 4.
rev. 1.5 / apr. 2008 34 hy5rs123235bfp figure 20: consecutive write to write note: 1. di b, etc. = data-in for column b, etc. 2. three subsequent elements of data-in are applied in the specified order following di b. 3. three subsequent elements of data-in are applied in the specified order following di n. 4. burst of 4 is shown. 5. each write command may be to any bank of the same device. 6. write latency is set to 3.
rev. 1.5 / apr. 2008 35 hy5rs123235bfp figure 21: nonconsecu tive write to write note: 1. di b, etc. = data-in for column b, etc. 2. three subsequent elements of data-in are applied in the specified order following di b. 3. three subsequent elements of data-in are applied in the specified order following di n. 4. a burst of 4 is shown. 5. each write command may be to any banks. 6. write latency set to 3.
rev. 1.5 / apr. 2008 36 hy5rs123235bfp figure 22: random write cycles note: 1. di b, etc. = data-in for column b, etc. 2. b', etc. = the next data-in following di b, etc., according to the specified burst order. 3. programmed burst length = 4 case is shown. 4. each write command may be to any banks. 5. last write command will have the rest of the nibble on t8 and t8n. 6. write latency is set to 3.
rev. 1.5 / apr. 2008 37 hy5rs123235bfp figure 23: write to read timing note: 1. di b = data in for column b 2. three subsequent elements of data in are applied following d1 b 3. twtr is referenced from the first positive ck edge after the last data in 4. the read and write commands may be to any bank. 5. write latency is set to 1 6. the 4n prefetch architecture requires a 2- clock write-to-read turn around time (twtr).
rev. 1.5 / apr. 2008 38 hy5rs123235bfp figure 24: write to precharge note: 1. di b = data-in for column b. 2. three subsequent elements of data-in are applied in the specified order following di b. 3. a burst of 4 is shown. 4. a8 is low with the write comm and (auto precharge is disabled). 5. write latency is set to 3.
rev. 1.5 / apr. 2008 39 hy5rs123235bfp precharge the precharge command (shown in figure25) issused to deactivate the open row in a particular bank or the open row in all banks . the bank(s) will be available for a subsequent row access some specified time (trp) after the pr echarge command is issued. inpu t a8 determines whether one or all banks are to be precharged, and in the case where only on e bank is to be precharged, inputs ba0-b a2 select the bank. when all banks are to be precharged, inputs ba0-ba2 are treated as ?don?t care.? once a bank has been pre- charged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. figure 25: precharge command power-down (cke not active) unlike sdr sdrams, gddr3 sdrams require cke to be active at all times that an access is in prog ress: from the issuing of a read or write command until completion of the burst. for reads, a burst completion is defined when the read postamble is satisfied; for writes, a burst completion is defined when the write postamble is satisfied. power-down (shown in figure26, power-down, on page38) is entered when cke is registered low. if power-down occu rs when all banks are idle, this mode is referred to as precha rge power-down; if power-down occurs when there is a row active in any banks, this mode is referred to as active power-down. enteri ng power-down deactivates the input and output buffers, excluding ck , ck# and cke. for maximum power savings, the user also has the option of disabling the dll prior to entering power-down. in that case, the dll must be enabled and reset after exiting pow er- down, and 5k clock cycles must occur before a read command can be issued. however, power-down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the dll-disabled power-dow n mode. while in power-down, cke low and a stable clock signal must be maintained at the inputs of the gddr3 sdram, while all other input signals are ?don?t care.? the po wer-down state is synchronously exited when cke is registered high (in conjunction with a nop or deselect command). a valid executable command may be applied four clock cycles later.
rev. 1.5 / apr. 2008 40 hy5rs123235bfp figure 26: power-down table 8: truth table - cke notes: 1~4; notes appear below table note: 1. cken is the logic state of cke at clock edge n; cken-1 was the state of cke at the previous clock edge. 2. current state is the state of the gddr 3 sdram immediately prior to clock edge n. 3. commandn is the command registered at clock edge n, and actionn is a result of commandn. 4. all states and se quences not shown are illegal or reserved. 5. deselect or nop commands should be issued on any clock edges occurring during the txsr period. a minimum of 5k clock cycles is needed for the dll to lock before applying a read command if the dll was disabled. cken-1 cken current state commandn actionn notes l l power-down x maintain power-down l l self refresh x maintain self refresh l h power-down deselect or nop exit power-down l h self refresh deselect or nop exit self refresh 5 h l all banks idle deselect or nop precharge power-dwon entry h l bank(s) active deselect or nop active power-down entry h l all banks idle auto refresh self refresh entry h h see truth table 3
rev. 1.5 / apr. 2008 41 hy5rs123235bfp table 9: truth table - current st ate bank n - com mand to bank n notes: 1~3; notes appear below table note: 1. this table applies when cken-1 was high and cken is high (see truth table 2) an d after txsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are t hose allowed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses a re in progress. read: a read burst has been init iated, with auto precharge disabled. write: a write burst has been init iated, with auto precharge disabled. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands t o the other bank are determined by its current state and tabl e9, and according to table10. precharging: starts with registrat ion of a precharge command and ends wh en trp is met. once trp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when trcd is met. once trcd is met, the bank will be in the ?row active? state. read w/auto-precharge enabled: starts with registration of a read command with auto precharge enabled and ends when trp has been met. once trp is me t, the bank will be in the idle state. write w/auto-precharge enabled: starts with registration of a write command with auto precharge enabled and ends when trp has been met. once trp is me t, the bank will be in the idle state. 5. the following states must not be inte rrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when trc is met. once trc is met, the gddr3 x32 will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when tmrd has been met. once tmrd is met, the gddr3 x32 will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when trp is met. once trp is met, all banks will be in the idle state. read or write: starts with the registation of the active command and ends the last valid data nibbl e. 6. all states and se quences not shown are illegal or reserved. 7. not bank-specific; requires that all bank s are idle, and bursts are not in progress. 8. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 10. requires appropriate dm masking. 11. a write command may be applied afte r the completion of the read burst current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/con tinue previous operation) l l h h active (select and activate row) idle l l l h auto refresh 4 ll l lload mode register 4 row active l h l h read (select co lumn and start read burst) 6 l h l l write (select column and start write burst) 6 l l h l precharge (deactivate row in bank or banks) 5 read (auto pre- charge disabled) l h l h read (select column and start new read burst) 6 l h l l write (select column and start write burst) 6, 8 ll h lprecharge ( truncate read burst , start precharge )5 write (auto pre- charge disabled) l h l h read (select column and start read burst) 6, 7 l h l l write (select column and start new write burst) 6 ll h lprecharge ( truncate write burst, start precharge )5, 7
rev. 1.5 / apr. 2008 42 hy5rs123235bfp table 10: truth table - current state bank n - command to bank m notes: 1~5; notes appear below table note: 1. this table applies when cken-1 was high and cken is high (see table9) and after txsnr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands sh own are those allowed to be issued to ba nk m, assuming that bank m is in such a state that the given co mmand is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses a re in progress. read: a read burst has been init iated, with auto precharge disabled. write: a write burst has been init iated, with auto precharge disabled. read with auto precharge enabled: see following text write with auto precha rge enabled: see following text current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/con tinue previous operation) idle x x x x any command otherwise allowed to bank m row activat- ing, active, or precharging l l h h active (select and activate row) l h l h read (select column and start read burst) 6 l h l l write (select column and start write burst) 6 ll h lprecharge read (auto precharge dis- abled) l l h h active (select and activate row) l h l h read (select column and start new read burst) 6 l h l l write (select column and start write burst) 6 ll h lprecharge write (auto precharge dis- abled) l l h h active (select and activate row) l h l h read (select column and start read burst) 6, 7 l h l l write (select column and start new write burst) 6 ll h lprecharge read(with auto pre- charge) l l h h active (select and activate row) l h l h read (select column and start new read burst) 6 l h l l write (select column and start write burst) 6 ll h lprecharge write(with auto pre- charge) l l h h active (select and activate row) l h l h read (select column and start read burst) 6 l h l l write (select column and start new write burst) 6 ll h lprecharge
rev. 1.5 / apr. 2008 43 hy5rs123235bfp 3a. the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precha rge, the precharge period is defined as if the same burst was exe- cuted with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all of th e data in the burst. for write with auto precharge, the precharge period begins when twr ends, with twr measured as if auto pre- charge was disabled. the access period starts with registration of the command and ends where the precharge period (or trp) begins. during the precharge period of the read with auto precharge en abled or write with auto pr echarge enabled states, active , precharge, read and write commands to the other bank may be appl ied. in either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). 3b. the minimum delay from a read or write command with au to precharge enabled, to a command to a different bank is sum- marized below. 4. auto refresh and load mode register command s may only be issued when all banks are idle. 5. all states and se quences not shown are illegal or reserved. 6. reads or writes listed in the command/action column includ e reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 7. requires appropriate dm masking. table 11: minimum delay between comma nds to different banks with auto precharge enabled note: cl = cas latency (cl) rounded up to the next integer. bl = burst length. wl = write latency. 1) write data connot be driven onto the dq bus for 2 clocks afte r the read data is off the bus.(refer to fig16. on the page29) from command to command minimum delay (with concurrent auto precharge) write with auto precharge read or read with auto precharge [wl + (bl/2)] tck + twtr write or write with auto precharge (bl/2) tck precharge 1 tck active 1 tck read with auto precharge read or read with auto precharge (bl/2) * tck write or write with auto precharge [cl + (bl/2) + 2 - wl] * tck 1) precharge 1 tck active 1 tck
rev. 1.5 / apr. 2008 44 hy5rs123235bfp absolute maximum ratings* voltage on vdd supply relative to vss .............................................-0.5v to +2.5v voltage on vddq supply relative to vss .............................................-0.5v to +2.5v voltage on vref and inputs relative to vss .............................................-0.5v to +2.5v voltage on i/o pins relative to vss ....................................-0.5v to vddq +0.5v max junction temperature, tj ...........................+125 ? storage temperature (plastic)................-55 ? to +150 ? power dissipation..........................................................tbd short circuit output current......................................50ma * stresses greater than those listed may ca use permanent damage to the device. this is a stress rating only , and functional ope ration of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 12: thermal characteristics note: 1. measurement procedures for each parameter must follow standa rd procedures defined in the current jedec jesd-51 standared. 2. theta_ja and theta_jc must be measur ed with the high effective thermal cond uctivity test board defined in jesd51-7 3. airflow information must be deocumented for theta_ja. 4. theta_ja should only be used for comparing the thermal perf ormance of signle packages and not for system related junction. 5. theta_ja is the natural convection junction-to-ambient air th ermal resistance measured in on e cubic foot sealed enclosure as described in jesd-51. the environment is sometimes referred to as ?still-air? although natural convection causes the air to move. 6. theta_jc case surface is defined as the ?outside surface of the packag e (case) closest to the chip mounting area when that s ame surface is properly hear sunk? so as to mini mize temperature variation across that surface. 7. test condition : voltage 2.15v(max imum voltage) / frequency : 1ghz parameter description value unit notes tc case temperature 115.0 ? 7 tj junction temperature 124.2 ? 7 theta_ja thermal resistance junction to ambient 31.5 ? / w 1,2,3,4,5,7 theta_jc thermal resistan ce junction to case 4.9 ? / w 1,2,6,7
rev. 1.5 / apr. 2008 45 hy5rs123235bfp table 13: dc electrical characte ristics and operating conditions (recommended operating conditions; 0 ? <= tc <= 85 ? ) note : 1. it supports 1g/1.2ghz speed at hy5rs123235bfp-1/ 08. 2. it supports 500/700/900mhz speed at hy5rs123235bfp-2 / 14 / 11. 3. it supports 550/700mhz speed at hy5rc123235bfp-18l / 14l. table 14: ac input operating (recommended operating conditions; 0 ? <= tc <= 85 ? ) parameter/condition symbol min typ max units remark supply voltage / i/o supply voltage vdd/ vddq 1.95 2.05 2.15 v 1 1.7 1.8 2.15 v 2 1.455 1.5 1.545 v 3 i/o reference voltage vref 0.69xvddq 0.70xvddq 0.71xvddq v input high (logic 1) voltage vih(dc) vref+0.15 - - v input low (logic 0) voltage vil(dc) - - vref-0.15 v input leakage current any input 0v <= vin <= vdd (all other pins not under test = 0v) ii -5 - 5 ua output leakage current (dqs are disabled; 0v <= vout <= vddq) ioz -5 - 5 ua output logic low vol(dc) - - 0.76 v parameter/condition symbol min typ max units input high (logic 1) voltage; dq vih(ac) vref+0.250 - - v input low (logic 0) voltage; dq vil(ac) - - vref-0.250 v clock input differential voltage; ck and ck# vid(ac) 0.22 - vddq+0.3 v clock input crossing point voltage; ck and ck# vix(ac) vref-0.15 - vref+0.15 v
rev. 1.5 / apr. 2008 46 hy5rs123235bfp output impedance and termination dc electrical characteristics the driver and termination impedances are determined by applying vddq /2 nominal (0.9v) at the corresponding input or output and by measuring the current flowing into or out of the device. vddq is set to the nominal 1.8v. ? ioh is the current flowing out of dq when the pull-up transistor is activated and the dq termination is disabled ? iol is the current flowing out of dq when the pull-down transistor is activated and the dq termination is disabled ? itcah(zq/2) is the current flowing out of the termination of commands and addresses for a zq/2 termination value ? itcah(zq) is the current flowing out of the terminatio n of commands and addresses for a zq termination value. ? itdqh(zq/4) is the current flowing out of the termination of the dqs for a zq/4 termination value. ? itdqh(zq/2) is the current flowing out of the termination of the dqs for a zq/2 termination value note: measurement performed with vddq = 1.8v (n ominal) and by applying vddq/2 (0.9v) at the corresponding input or output. (0 ? <= tc <= +85 ? ) table 15: driver and termination dc characteristics (1.8v version) parameter zq value 200 240 280 ohm min max min max min max units notes ioh zq/6 24.5 30.0 20.5 25.0 17.5 21.4 ma iol zq/6 24.5 30.0 20.5 25.0 17.5 21.4 ma itcah (zq/2) zq/2 8.2 10.0 6.8 8.3 5.8 7.1 ma itcah (zq) zq 4.1 5.0 3.4 4.2 11.7 14.3 ma itdqh (zq/4) zq/4 16.4 18.0 13.6 16.7 11.7 14.3 ma itdqh (zq/2) zq/2 8.2 10.0 6.8 8.3 5.8 7.1 ma
rev. 1.5 / apr. 2008 47 hy5rs123235bfp figure 27: input and output voltage waveform
rev. 1.5 / apr. 2008 48 hy5rs123235bfp table 16: clock input operatin g conditions (1.8v version) figure 28: clock input note: 1. this provides a minimum of 1.16v to a ma ximum of 1.36v, and is always 70% of vddq. 2. ck and ck# must cr oss in this region. 3. ck and ck# must meet at least vin(dc) min when static and is centered around vmp(dc). 4. ck and ck# must have a mi nimum 600mv peak-to-peak swing. 5. ck or ck# may not be more positive than vddq + 0.5v or lower than 0.22v. 6. for ac operation, all dc clock requirements must also be satisfied. 7. numbers in diagram reflect nominal values. parameter/condition symbol min typ max units clock input midpoint voltage; ck and ck# v mp (dc) 1.16 1.26 1.36 v clock input voltage level; ck and ck# v in (dc) 0.42 - v ddq +0.3 v clock input differential voltage; ck and ck# v id (dc) 0.22 v ddq v clock input differential voltage; ck and ck# v id (ac) 0.22 v ddq +0.3 v clock input crossing point voltage; ck and ck# v ix (ac) v ref -0.15 0.70xv ddq v ref +0.15 v
rev. 1.5 / apr. 2008 49 hy5rs123235bfp table 17: capacitance note: 13; notes appear on pages 49,50 table 18: idd specif ications and conditions (units : ma) note:1-5, 10, 12, 14, 40; notes on page 49,50; 0 ? <= tc <= 85 ? note : . ?-18l/-14l? means low voltage so its cu rrent is measured at 1.545max voltage. . hy5rs123235bfp-2/-14/-11 is standardized by 1.9max voltage. hy5rs123235bfp-1/-08 is standardized by 2.15max voltage. parameter symbol min max units notes delta input/output capacitance: dqs, dqs, dm dcio - 0.20 pf 24 delta input capacitance: command and address dci1 - 0.40 pf 29 delta input capacitance: ck, ck# dci2 - 0.10 pf 29 input/output capacitance: dqs, dqs, dm cio 1.5 3.5 pf input capacitance: command and address ci1 1.0 3.0 pf input capacitance: ck, ck# ci2 1.0 3.0 pf input capacitance: cke ci3 1.0 3.0 pf parameter/condition symbol max notes -18l -14l -2 -14 -11 -1 -08 operating current: one bank; active-precharge; trc (min); tck = tck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle; wl=6 idd0 160 180 350 420 550 600 650 22, 46 operating current: one bank; active read precharge; burst = 4; trc (min); tck = tck (min); address and control inputs changing once per clock cycle; i(out) =0ma; wl=6 idd1 160 180 350 420 550 600 650 22, 46 precharge power-down standby current: all banks idle; power-down mode; tck = tck (min); cke= low idd2p 40 50 80 90 140 160 180 32 idle standby current: cs# = high; all banks idle; tck = tck (min); cke = high; inputs changing once per clock cycle idd2n 100 120 170 200 290 310 350 active power-down standby current: one bank active; power-down mode; tck = tck (min); cke= low; wl=6 idd3p 50 60 95 110 165 180 195 32 active standby current: cs# = high; cke = high; one bank; active precharge; trc = tras (max); tck = tck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle;wl=6 idd3n 110 130 280 320 450 480 530 22 operating current: burst = 4; reads; continuous burst; one bank active; address and co ntrol inputs changing once per clock cycle; tck = tck (min); i(out)=0ma; wl=6 idd4r 440 480 650 825 1100 1250 1380 operating current: burst = 4; writes; continuous burst; one bank active; address and co ntrol inputs changing once per clock cycle; tck = tck (min); dq, dm, and dqs inputs changing twice pe r clock cycle; wl=6 idd4w 460 500 655 830 1180 1300 1420 auto refresh current trfc (min) idd5a 280 300 400 480 550 600 660 22 trfc = 3.9us idd5b 120 150 197 235 276 298 324 27 self refresh current: cke <= 0.2v idd6 10 10 20 20 20 35 35 11
rev. 1.5 / apr. 2008 50 hy5rs123235bfp table 19: electrical characteristics and ac operating conditions notes: 1-5,14-16, 33,40; notes on pages 49.50; 0 ? <= tc <=85 ? ac characteristics parameter -18l -14(l) -2 unit note parameter symbol min max min max min max dqs out access time from ck tdqsck -0.35 +0.35 -0.26 +0.26 -0.35 +0.35 tck ck high-level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck 30 ck low-level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck 30 clock cycle time cl=9 tck - - 1.4 3.3 - - ns 33, 40, 48 cl=7 tck 1.8 3.3 - - 1.8 3.3 ns 33, 40, 48 write latency twl 1,2,3,4, 5,6 1,2,3,4, 5,6 1,2,3,4, 5,6 tck 43 dq & dm input hold time relative to dqs tdh 0.25 0.18 0.25 ns 26, 31 dq & dm input setup time relative to dqs tds 0.25 0.18 0.25 ns 26, 31 active termination setup time tats 10 10 10 ns active termination hold time tath 10 10 10 ns dqs input high pulse width tdqsh 0.48 0.52 0.48 0.52 0.48 0.52 tck dqs input low pulse width tdqsl 0.48 0.52 0.48 0.52 0.48 0.52 tck dqs-dq skew tdqsq -0.225 +0.225 -0.160 +0.160 -0.225 +0.225 ns 25, 26 write command to first dqs latching transition tdqss wl-0.2 wl+0.2 wl-0.2 wl+0.2 wl-0.2 wl+0.2 tck dqs falling edge to ck rising . setup time tdss 0.25 0.25 0.25 tck dqs falling edge from ck rising . hold time tdsh 0.25 0.25 0.25 tck half strobe period thp tcl min or tch min tcl min or tch min tcl min or tch min tck 34 data output hold time from dqs tqh thp- 0.225 thp-0.16 thp- 0.225 ns data-out high-impedance window from ck/ck# thz 0.3 0.3 0.3 ns 18 data-out low-impedance window fromck/ck# tlz 0.3 0.3 0.3 ns 18 address and control input hold time tih 0.5 0.35 0.5 ns 14 address and control input setup time tis 0.5 0.35 0.5 ns 14 address and control input pulse width tipw 1.3 1.0 1.3 ns load mode register command cycle time tmrd 4 6 4 tck 44
rev. 1.5 / apr. 2008 51 hy5rs123235bfp ac characteristics parameter -18(l) -14(l) -2 unit note parameter symbol min max min max min max average periodic refresh interval trefi 3.9 3.9 3.9 us 23 dqs read preamble trpre 0.4 0.6 0.4 0.6 0.4 0.6 tck 46 dqs read postamble trpst0.40.60.40.60.40.6tck dqs write preamble twpre0.40.60.40.60.40.6tck dqs write preamble setup time twpres 0 0 0 ns 20, 21 dqs write postamble twpst0.40.60.40.60.40.6tck19, 37 jitter over 1~6 clock cycle error tj - 0.03 - 0.03 - 0.03 tck cycle to cycle duty cycle error tdcerr - 0.03 - 0.03 - 0.03 tck rise and fall times of ck tr, tf-0.2-0.2-0.2tck
rev. 1.5 / apr. 2008 52 hy5rs123235bfp table 19: electrical characteristics and ac operating conditions notes: 1-5,14-16, 33,40; notes on pages 49.50; 0 ? <= tc <=85 ? ac characteristics parameter -11 -1 -08 unit note parameter sym- bol min max min max min max dqs-out access time from ck tdqsck -0.22 +0.22 -0.2 +0.2 -0.2 +0.2 tck ck high-level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck 30 ck low-level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck 30 clock cycle time cl=11 tck - - - - 0.8 3 ns 33, 40, 48 cl=11 tck - - 1 3 - - ns 33, 40, 48 cl=10 tck 1.1 3.3 - - - - ns 33, 40, 48 write latency twl 1,2,3, 4,5,6 1,2,3, 4,5,6 1,2,3, 4,5,6 tck 43 dq & dm input hold time relative to dqs tdh 0.15 0.13 0.125 ns 26, 31 dq & dm input setup time rela- tive to dqs tds 0.15 0.13 0.125 ns 26, 31 active termination setup time tats 10 10 10 ns active termination hold time tath 10 10 10 ns dqs input high pulse width tdqsh 0.48 0.52 0.48 0.52 0.48 0.52 tck dqs input low pulse width tdqsl 0.48 0.52 0.48 0.52 0.48 0.52 tck dqs-dq skew tdqsq -0.13 0.13 -0.12 0.12 -0.11 0.11 ns 25, 26 write command to first dqs latching transition tdqss wl-0.2 wl+0.2 wl-0.2 wl+0.2 wl-0.2 wl+0.2 tck dqs falling edge to ck rising . setup time tdss 0.25 0.25 0.25 tck dqs falling edge from ck rising . hold time tdsh 0.25 0.25 0.25 tck half strobe period thp tcl min or tch min tcl min or tch min tcl min or tch min tck 34 data output hold time from dqs tqh thp-0.13 thp-0.12 thp-0.11 ns data-out high-impedance win- dow from ck/ck# thz -0.3 -0.3 -0.3 ns 18 data-out low-impedance win- dow fromck/ck# tlz -0.3 -0.3 -0.3 ns 18 address and control input hold time tih 0.28 0.27 0.24 ns 14 address and control input setup time tis 0.28 0.27 0.24 ns 14 address and control input pulse width tipw 0.8 0.7 0.7 ns load mode register com- mand cycle time tmrd 7 7 7 tck 44
rev. 1.5 / apr. 2008 53 hy5rs123235bfp table 19: electrical characteristics and ac operating conditions notes: 1-5,14-16, 33,40; notes on pages 49.50; 0 ? <= tc <=85 ? ac characteristics parameter -11 -1 -08 unit note parameter symbol min max min max min max dqs read preamble trpre 0.4 0.6 0.4 0.6 0.4 0.6 tck 46 dqs read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs write preamble twpre 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs write preamble setup time twpres 0 0 0 ns 20, 21 dqs write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 19, 37 jitter over 1~6 clock cycle error tj - 0.03 - 0.03 - 0.03 tck cycle to cycle duty cycle error tdcerr - 0.03 - 0.03 - 0.03 tck rise and fall times of ck tr, tf - 0.2 - 0.2 - 0.2 tck data out zq gddr3 60 ? 240 ? 10pf ac timing reference load ( refer to note3 on page49) timing reference point vddq vddq
rev. 1.5 / apr. 2008 54 hy5rs123235bfp notes: 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electrical ac and dc characteristics may be conduc ted at nominal reference/supply voltage leve ls, but the related specifications and device operat ion are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load of 10pf terminated with 60 ? to vddq. the output timing reference voltage level for single ended signals is the cross po int with vref (=0.7*vddq nominal). 4. ac timing and idd tests may use a vil-to-vih swing of up to 1.0v in the test environment, but input timing is still referenc ed to vref (or to the crossing point for ck/ck# ), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 3v/ns in the range between vil(ac) a nd vih(ac). 5. the ac and dc input level specifications are a pseudo open drain design for improved high-speed signaling. 6. vref is expected to equal 70 percent of vddq for the transmitting device and to track variations in the dc level of the same . peak- to-peak noise on vref may not exceed ? 2 percent of the dc value. thus, from 70% of vddq, vref is allowed ? 25mv for dc error and an additional ? 25mv for ac noise. 7. needed to further definitions. 8. vid is the magnitude of the difference between the input level on ck and the input level on ck#. 9. the value of vix is expected to equal 70 percent of vddq for the transmitting device and must track variations in the dc lev el of the same. 10. idd is dependent on output loading and cycle rates. specified values are obtained with minimu m cycle time at minium cas latency and does not include the on-die terminat ion current. outputs are open during idd measurements. 11. enables on-chip refresh and address counters. 12. idd specifications are tested after the device is properly initialized. 13. this parameter is sampled. vdd = 1.8v, vddq = 1.8v, vref = vss, f = 1 mhz, ta =25 ? , vout(dc) = 0.75v, vddq, vout (peak to peak)= 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 14. command/address input slew rate = 3 v/ns. if the slew rate is less than 3 v/ns, timing is no longer referenced to the midpo int but to the vil(ac) maximum and vih(ac) minimum points. 15. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross; the input refere nce level for signals other than ck/ck# is vref. 16. inputs are not recognized as valid until vref stabilizes. exception: during the period before vref stabilizes, mf, cke <= 0 .3 x vddq is recognized as low. 17. not used in this specification. 18. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not reference d to a specific voltage level, but specify when the devi ce output is no longer drivin g (hz) or begins driving(lz). 19. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter , but system performance(bus turn-around) will degrade accordingly. 20. this is not a device limit. the device will operate with a ne gative value, but system performance could be degraded due to bus turnaround. 21. it is recommended that wdqs be valid (h igh orlow) on or before the write command. 22. min (trc or trfc) for idd measurements is the smallest multiple of tck that meet s the minimum absolute value for the respec tive parameter. trasmax for idd measurements is the largest multiple of tck that meets the maximum absolute value for tras. 23. the refresh period is 8k every 32ms. this equates to an average re fresh rate of 3.9us. 24. the i/o capacitance per dqs and dq byte/group will not diffe r by more than this maximum amount for any given device. 25. the valid data window is derived by achieving other specific ations . tdqhp and tdqsq. the data valid window derates in dire ct proportion to the strobe duty cycle and a practical data valid window can be derived. the strobe is allowed a maximum dut y cycle variation of 48:52. functionality is uncertain when operatin g beyond a 48:52 ratio. 26. referenced to each output group: rdqs0 with dq0.dq7, rdqs1 with dq8.dq15, rdqs2 with dq16.dq23, and rdqs with dq24.dq31.
rev. 1.5 / apr. 2008 55 hy5rs123235bfp 27. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period (trfc [min]) else cke is low (e.g., during standby). 28. the dc values define where the input slew rate requirements are imposed, and the input sign al must not violate these levels in order to maintain a valid level. the inputs require the ac value to be achieved during signal transition edge, and the dr iver should achieve the same slew rate through the ac values. 29. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. ck and ck# input slew rate must be >= 6 v/ns. 31. dq and dm input slew rates must not deviate from wdqs by more than 10 percent. if the dq/dm/wdqs slew rate is less than 3 v/ns, timing is no longer referenced to the midpoint but to the vil(ac) maxi mum and vih(ac) minimum points. 32. vdd must not vary more than 4 percent if cke is not active whil e any bank is active. 33. the clock is allowed up to ? 90ps of jitter. each timing parameter is allowed to vary by the same amount. 34. thp (min) is the lesser of tdqsl minimum and tdqsh minimum ac tually applied to the device ck and ck# inputs, collectively during bank active. 35. for reads and writes with auto precharge the gddr3 device will hold off the internal prec harge command until tras (min) has been satisfied. 36. the last rising edge of wdqs after the write postamble must be driven high by th e controller.wdqs cannot be pulled high by the on-die termination alone. for th e read postamble the gddr3 will drive the last rising edge of the read postamble. 37. the voltage levels used are derived from the referenced test load. in practi ce, the voltage levels obtained from a properly termi nated bus will provide significantly different voltage values. 38. vih overshoot: vih (max) = vddq + 0.5v for apulse width <= 500ps and the pulse width cannot be greater than 1/3 of the cycl e rate. vil under-shoot: vil (min) = 0.0v for a pulse widt h <= 500ps and the pulse width cannot be greater than 1/3 ofthe cy cle rate. 39. the dll must be reset wh en changing the frequency, followed by 5k clock cycles. 40. junction temperature is a function of total device power dissipation and device mounting environment. measured per semi g38 - 87. 41. the thermal resistance data is based on a number of samples fr om multiple lots and should be viewed as a typical number. th ese parameters are not tested in producti on or just guaranteed by the simulation methods. 42. the write latency can be set from 1 to 6 clocks but can never be less than 2ns for latencies of 1 and 3clocks. when the wri te latency is set to 1 or 3 clocks,the input buffers are al ways on, reducing the latency but adding power. when the write la tency is set to 4 or 6 clocks the inpu t buffers are turned on during the write co mmands for lower power operation and can never be less than 7.5ns. 43. we?ll try to cut these values for positive timing budget of 800mhz operations 44. minimum of +9 cycles are needed to read commands. 45. 8 banks device sequential bank activation restriction: no mo re than 4 banks may be activate d in a rolling tfaw(four actvite wind ow). tfaw=4th banks act + trrd*2=(trrd*5). converting to clocks is done by dividing tfaw by tck and rounding up to next integer. 46. in here, trpre means, low drive period of rdqs prior to th e valid high rising edge. it doesn't include the high drive peri od prior to low drive. 47. wr_a (write recovery time for autoprecharge) in clock cycles is calculated by dividing twr (in ns) and rounding up to the n ext integer (wr[cycles] = twr(ns)/tck(ns)). th e mode register must be programmed to this value. 48. tck_max = 3.3ns at cl7~10, tck_max = 3ns at cl11
rev. 1.5 / apr. 2008 56 hy5rs123235bfp table 20: electrical characteristics usages as clock phase note) *: 1. it?s only reference for customers who woul d like to use 700mhz(-14) part for 600mhz operation and 900mhz(-11) part of 800mhz operation an d please use cl=8 for (-16) operat ion and cl=10 for (-12) operation. 2. ?-18l/-14l? means low voltage so its value is measured at 1.545max voltage. 3. hy5rs123235bfp-2/-14/-11 is standardized by 1.9max voltage and hy5rs123235bfp-1/-08 is standardized by 2.15max voltage. ac characteristics parameter -18l -16(l)* -14(l) -2 -12* -11 -1 -08 unit parameter sym- bol min max min max min max min max min max min max min max min max active to precharge command tras 17 70kns 19 70kns 22 70kns 15 70kns 25 70kns 28 70kns 70kns 28 70kns tck active to active/auto refresh command period trc 24 - 28 - 31 - 22 - 35 - 40 - -39-tck auto refresh command period trfc30-31-39-27-45-50- -50-tck active to read delay trcdr 8 - 10 - 11 - 8 - 12 - 13 - 14 - 14 -tck active to write delaytrcdw5-6-7-5 8-9-9- 9 -tck precharge command period trp7-8-9-7-10-11-12- 12 -tck active bank a to active bank b com- mand trrd5-6-7-5-8-9- -9-tck bank active restriction rolling window tfaw28-32-35-25-40-44-48-48-tck write recovery time twr 7 - 8 - 9 - 7 - 10 - 12 - 12 - 12 - tck internal write to read command delay twtr4-5-6-4-7-8- -7-tck write recovery time + precharge command period tdal14-16-18-14-20-22-24- -tck exit self refresh to read command txsrd5k5k5k5k5k-5k 5k 5ktck exit self refresh to non-read command txsnr 300 - 300 - 300 - 300 - 300 - 300 - 300 - 300 - tck power-down exit time tpdex 4tcjk +tis 5tcjk +tis 5tcjk +tis 4tcjk +tis 6tcjk +tis - 7tcjk +tis 7tcjk +tis 7tcjk +tis tck refresh interval time tref-3.9-3.9-3.9-3.9-3.9-3.9-3.9-3.9us
rev. 1.5 / apr. 2008 57 hy5rs123235bfp i/o and odt values the driver and termination impedances are derived from the following test conditions under worst case process corners: 1. nominal 1.8v (vdd/vddq) 2. power the gddr3 device and calibrate the output driv ers and termination to eliminate process variation at 25 ? . 3. reduce temperature to 10 ? recalibrate. 4. reduce temperature to 0 ? and take the fast corner measurement. 5. raise temperature to 75 ? and recalibrate 6. raise temperature to 85 ? and take the slow corner measurement i/o impedances pull-down characteristic at 40 ohms pull-up ch aracteristic at 40ohms voltage (v) min max voltage (v) min max 0.1 2.144 3.366 0.1 -2.377 -2.946 0.2 4.268 6.516 0.2 -4.705 -5.829 0.3 6.373 9.454 0.3 -6.984 -8.644 0.4 8.449 12.185 0.4 -9.283 -11.383 0.5 10.505 14.715 0.5 -11.524 -14.038 0.6 12.542 17.051 0.6 -13.803 -16.599 0.7 14.540 19.400 0.7 -16.015 -19.051 0.8 16.509 21.828 0.8 -18.285 -21.630 0.9 18.449 24.219 0.9 -20.302 -24.143 1.0 20.341 26.580 1.0 -22.223 -26.605 1.1 22.203 28.913 1.1 -24.066 -29.005 1.2 24.017 31.222 1.2 -25.773 -31.353 1.3 25.783 33.508 1.3 -27.344 -33.619 1.4 27.480 35.813 1.4 -28.683 -35.803 1.5 29.119 38.213 1.5 -29.731 -37.883 1.6 30.671 40.551 1.6 -30.691 -39.882 1.7 31.387 42.900 1.7 -31.544 -42.003 1.8 31.648 45.176 1.8 -32.311 -44.063
rev. 1.5 / apr. 2008 58 hy5rs123235bfp on die termination values pull-up characteristic at 60ohms pull-up characteri stic at 120ohms pull-up characteristic at 240ohms voltage (v) min max voltage (v) min max voltage (v) min max 0.1 -1.58 -1.96 0.1 -0.79 -0.98 0.1 -0.40 -0.49 0.2 -3.14 -3.89 0.2 -1.57 -1.94 0.2 -0.78 -0.97 0.3 -4.66 -5.76 0.3 -2.33 -2.88 0.3 -1.16 -1.44 0.4 -6.19 -7.59 0.4 -3.09 -3.79 0.4 -1.55 -1.90 0.5 -7.68 -9.36 0.5 -3.84 -4.68 0.5 -1.92 -2.34 0.6 -9.20 -11.07 0.6 -4.60 -5.53 0.6 -2.30 -2.77 0.7 -10.68 -12.70 0.7 -5.34 -6.35 0.7 -2.67 -3.18 0.8 -12.19 -14.42 0.8 -6.09 -7.21 0.8 -3.05 -3.60 0.9 -13.53 -16.10 0.9 -6.77 -8.05 0.9 -3.38 -4.02 1.0 -14.82 -17.74 1.0 -7.41 -8.87 1.0 -3.70 -4.43 1.1 -16.04 -19.34 1.1 -8.02 -9.67 1.1 -4.01 -4.83 1.2 -17.18 -20.90 1.2 -8.59 -10.45 1.2 -4.30 -5.23 1.3 -18.23 -22.41 1.3 -9.11 -11.21 1.3 -4.56 -5.60 1.4 -19.12 -23.87 1.4 -9.56 -11.93 1.4 -4.78 -5.97 1.5 -19.82 -25.26 1.5 -9.91 -12.63 1.5 -4.96 -6.31 1.6 -20.46 -26.59 1.6 -10.23 -13.29 1.6 -5.12 -6.65 1.7 -21.03 -28.00 1.7 -10.51 -14.00 1.7 -5.26 -7.00 1.8 -21.54 -29.38 1.8 -10.77 -14.69 1.8 -5.39 -7.34
rev. 1.5 / apr. 2008 59 hy5rs123235bfp figure 29: data output timing - tdqsq, tqh and da ta valid window note: 1. tdqsq represents the skew between the ei ght dq lines and the respective rdqs pin. 2. tdqsq is derived at each rdqs edge and is not cumulative over time and begins with first dq transition and ends with the las t valid transition of dq. 3. tac is shown in the nominal case. 4. tdqhp is the lesser of tdqsl or tdqsh strobe transition collectively when a bank is active. 5. the data valid window is derived for ea ch rdqs transitions and is defined by tdv. 6. there are four rdqs pins for this device with rdqs0 in relati on to dq(0.7), rdqs1 in relation dq(8.15), rdqs2 in relation to dq(16.24), and rdqs3 in relation to dq(25.31). 7. this diagram only represents one of the four byte lanes.
rev. 1.5 / apr. 2008 60 hy5rs123235bfp figure 30: data output timing - ac note: 1. tac represents the relationship between dq, rdqs to the crossing of ck and ck#. figure 31: data input timing note: 1. tdsh (min) generally occurs during tdqss (min). 2. tdss (min) generally oc curs during tdqss (max).
rev. 1.5 / apr. 2008 61 hy5rs123235bfp package information pin a1 mark pin a1 mark 12 11 10 9 4 3 2 1 a b c d e f g h j k l m n p r t u 76 9 1 y 6 11 14 0.34+0.05 1.1 + 0.1 0.45+0.05 0.10 max 30 o 0.20+0.05 0.19 unit:mm
rev. 1.5 / apr. 2008 62 hy5rs123235bfp appendix a the following diagram shows the ge neral gddr3 driver and terminator self calibration flow for driver and terminator first calibrate pmos device against 240ohm resistor to vss via zq pin this calibrate one pmos leg to 240 ohms use 1 pmos leg for 240 ohm terminator use 2 pmos legs for 120 ohm terminator use 4 pmos legs for 60 ohm terminator use 6 pmos legs for 40 ohm pull up driver next calibrate one nmos le g against the already cali- brated 240 ohm pmos leg this calibrates one nmos leg to 240 ohms use 6nmos legs for 40 ohm driver 7%%2 pin%sjwfs xifousbotnjuujoh %2 pin 5fsnjobupsxifo sfdfjwjoh 7%%2 3fbeuppuifs 3bol 0vuqvu %bub 3fbe%bub &obcmf 0vuqvu%sjwfs 4usfohuidpouspm<> $pnqbjoups .bu di 7%%2 7%%2 pint 7442 8ifo.budi1nptmfhjtdbmjcsbufeuppint 4fmg$bmjcsbujpopg1npt-fh 1vmmfe-pxup7442 $pnqbjoups .budi 7442 7%%2 8ifo.budi/nptmfhjtdbmjcsbufeuppint 4fmg$bmjcsbujpopg/npt-fh 7%%2 4usfohuidpouspm <>
rev. 1.5 / apr. 2008 63 hy5rs123235bfp apendix b definition of terminology hereafter are defined terminologies us ed in the gddr3 sdram specification. although gddr3 might be operated in odt disable mode, it is not recommended and the specification describes the odt enable mode only. should a system be designed to operate the gddr3 in odt disable mode , the system should comprehend the effect of the discrepancies between this specification and its own design. if it is stated that a bus is in one of the following state, it should be interpreted as described. following are three terminologies defined for odt enable mode. - high{terminated}: a driver on the bus is driving the bus. one or more termination (odt) on the bus is turned-on. the voltage level of the bus would be nominally vddq. - hi-z{terminated}: no driver on the bus is driving the bus. one or more termination (odt) on the bus is turned-on. the voltage level of the bus would be nominally vddq. - low{terminated}: a driver on the bus is driving the bus. one or more termination (odt) on the bus is turned-on. the voltage level of the bus would be nominally vol(dc). corresponding terminologies for odt disable mode are defined below. as mentioned before, odt disable mode is no t an intended mode of operation. however, there exist situations where odt enable mode can not be guaranteed for a short period of time, like during power up, yet is indeed an intended mode of operation. - high{unterminated}: a driver on the bus is drivin g the bus. no termination on the bus is active. the voltage level of the bus would be nominally vddq. - hi-z{unterminated}: no driver on the bus is driv ing the bus. no termination on the bus is active. the voltag e level of the bus would be undefined, because the bus would be floating. - low{unterminated}: a driver on the bus is driving the bus. no termination on the bus is active. the voltage level of the bus would be nominally vssq.
rev. 1.5 / apr. 2008 64 hy5rs123235bfp appendix c boundary scan test mode general information the 512mb gddr3 incorporates a modified boun dary scan test mode as an optional feature. this mo de doesn?t operate in accor- dance with ieee standard 1149.11990. to save the current gddr3 ballo ut, this mode will scan the parallel data input and output the scanned data through wdqs0 pi n controlled by an addon pin, sen whic h is located at v4 of 136 ball package. disabling the scan feature it is possible to operate the 512mb gddr3 without using the boundary scan feature. sen(at v4 of 136ball package) should be tied low(vss) to prevent the device from entering the boundary scan mode. the other pins which are used for scan mode, res, mf, wdqs0 and cs# will be operating at normal gd dr3 functionalities when sen is deasserted. figure c-1: internal bloc k diagram(reference only)
rev. 1.5 / apr. 2008 65 hy5rs123235bfp table c-1: boundary scan (exit) order note: 1. when the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. since the other input of the mux for dm0 tied to gnd, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. two rfu balls (#56 and #57) in the scan order, will read as a logic?0?. table c-2: scan pin descriptions note: 1. when sen is asserted, no commands are to be executed by th e gddr3. this applies both to user commands and manufacturing commands which may exist while res is deasserted. 2. all scan functional ities are valid only after the appropriate power-up and initialization sequence. (res and cke, to set the odt of the c/a) 3. in scan mode, the odt for the address and control lines set to a nominal termination value of zq. the odt for dq?s will be d is abled. it is not necessary fo r the termination to be calibrated. 4. during the power-up and initialization sequence, zq pin should be maintained the connection to vssq through proper rq. 5. in a double-load clam-shell configuration, sen will be asserted to both devices. se parate two soe#?s should be provided to t op and bottom devices to access the scanned output. when either of the devices is in scan mode, soe# for the other device whic h is not in a scan will be disabled. bit# ball pin bit# ball pin bit# ball pin bit# ball pin 1d-3rdq0 18 g-9 ba1 35 p-10 rdqs2 52 k4 a0 2c-2dq2 19 h-9 we# 36 r-11 dq20 53 k-3 a2 3c-3dq3 20 h-10 ba2 37 r-10 dq21 54 k-2 a10 4b-2dq0 21 h-11 a5 38 t-11 dq22 55 l-4 a11 5b-3dq1 22 j-11 ck 39 t-10 dq23 56 j-3 rfu2 6a-4zq 23 j-10 ck# 40 t-3 dq31 57 j-2 rfu1 7b-10dq9 24 l-9 a7 41 t-2 dq30 58 h-2 a1 8b-11dq8 25 k-11 a8 42 r-3 dq29 59 h-3 ras# 9c-10dq11 26 k-10 a6 43 r-2 dq28 60 h-4 cke 10 c-11 dq10 27 k-9 a4 44 p-3 rdqs3 61 g-4 ba0 11 d-10 rdq1 28 m-9 a9 45 p-2 wdqs3 62 f-4 cas# 12 d-11 wdqs1 29 m-11 dq16 46 n-3 dm3 63 f-2 dq6 13 e-10 dm1 30 l-10 dq17 47 m-3 dq27 64 g-3 dq7 14 f-10 dq13 31 n-11 dq18 48 n-2 dq26 65 e-2 dq4 15 e-11 dq12 32 m-10 dq19 49 l-3 dq25 66 f-3 dq5 16 g-10 dq15 33 n-10 dm2 50 m-2 dq24 67 e-3 dm0 17 f-11 dq14 34 p-11 wdqs2 51 m-4 a3 ball symbol normal funtion type descriptions u-9 ssh res input scan shift. capture the data input from the pad at logic low and shift the data on the chain at logic high. f-9 sck cs# input scan clock. not a true clock, could be a single pulse or se ries of pulses. all scan inputs will be refer- enced to rising edge of the scan clock. d-2 sout wdqs0 output scan output. u-4 sen rfu input scan enable. logic high would enable the de vice into scan mode and will be disabled at logic low. must be tied to gnd when not in use. a-9 soe# mf input scan output enable. enables (registered low) and disables (regist ered high) sout data. this pin will be tied to vdd or gnd through a resistor (typic ally 1k) for normal operation. tester needs to overdrive this pin to guarantee the required input logic level in scan mode.
rev. 1.5 / apr. 2008 66 hy5rs123235bfp table c-3: scna dc electrical chara cteristics and operating conditions note: 1. the parameter applies only when sen is asserted. 2. all voltages referenced to gnd. figure c-2: scan capture timing figure c-3: scan shift timing table c-1: scan ac electrical charateristics parameter/conditionss symbol min max units input high(logic 1) voltage vih(dc) vref+0.15 - v input low(logic 0) volt age vil(dc) - vref-0.15 v parameters/conditions symbol min max units note clock sck sen ssh soe# pins under test tscs tses tsds tsdh va l i d not a true clock, but a sinlge pulse or series of pulses don?t care sck sen ssh soe# sout tses tscs tscs tsac tsoh transitioning data scan out bit 0 scan out bit 1 scan out bit 2 scan out bit 3
rev. 1.5 / apr. 2008 67 hy5rs123235bfp note: 1. the parameter applies only when sen is asserted. 2. scan enable should be issued earl ier than other scan commands by 10ns. figure c-4: scan in itialization sequence note: to set the pre-defined odt for c/a, a boundar y scan mode should be issu ed after an appropriate odt initialization sequence with res and cke signals clock cycle time tsck 40 - ns 1 scan command time scan enable setup time tses 20 - ns 1,2 scan enable hold time tseh 20 - ns 1 scan command setup time for ssh, soe# and sout tscs 14 - ns 1 scan command hold time for ssh, soe# and sout tsch 14 - ns 1 scan capture time scan capture setup time tsds 10 - ns 1 scan capture hold time tsdh 10 - ns 1 scan shift time scan clock to valid scan output tsac - 6 ns 1 scan clock to scan ou tput hold tsoh 1.5 - ns 1 parameters/conditions symbol min max units note va l i d va l i d vdd vddq vref res (ssh) cke sen sck soe# sout put tats tath tscs tsch tsds tsdh tses tscs tsds tsdh tscs tsch tsch tscs boundary scan test mode reset at power-up power-up: vdd stable t=200 s t=200 s don?t care

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